Single-charge tunneling device

ABSTRACT

A single-electron transistor ( 1 ) has an elongate conductive channel ( 2 ) and a side gate ( 3 ) formed in a 5 nm-thick layer ( 4 ) of Ga 0.98 Mn 0.02 As. The single-electron transistor ( 1 ) is operable, in a first mode, as a transistor and, in a second mode, as non-volatile memory.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation Application of U.S. Ser. No. 11/500,992, filed Aug. 9, 2006, entitled “Single-Charge Tunneling Device”, which application is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to a single-charge tunnelling device.

Single-charge tunnelling devices, such as single-electron transistors (SETs) and single-electron turnstiles, are well known in the art.

In single-electron transistors, transfer of an electron from a source lead to a drain lead via a small, weakly-coupled island is inhibited by Coulomb blockade due to the charging energy, E_(C), of the island. The charging energy E_(C)=e²/2C_(Σ), where C_(Σ) is the total capacitance of the island. Applying a voltage V_(G) to a gate electrode changes the electrostatic energy of the island to Q²/2C_(Σ)+QC_(G)V_(G)/C_(Σ) which is minimized when the charge on the island Q=ne equals −C_(G)V_(G)=Q₀. By tuning the continuous external variable Q₀to −(n+1/2)e, the charging energy associated with increasing the number of electrons on the island from n to n+1 vanishes and electrical current can flow between the leads. Changing the gate voltage then leads to oscillations in the source-drain current where each period corresponds to increasing or decreasing the charge state of the island by one electron.

Single-electron transistors are known which can operate at room temperature.

For example, “Room temperature operation of a single electron transistor made by the scanning tunnelling microscope nanooxidation process for the TiO_(x)/Ti system” by K. Matsumoto, M. Ishii, K. Segawa, Y. Oka, B. J. Vartanian and J. S. Harris Applied Physics Letters, vol. 68, p 34 (1996), which describes a metallic SET fabricated by a scanning tunnelling microscope nanooxidation process.

“Room-Temperature Demonstration of Low-Voltage and Tunable Static Memory Based on Negative Differential Conductance in Silicon Single-Electron Transistors” by M. Saitoh, H. Harata and T. Hiramoto, Applied Physics Letters, vol. 85, p 6233 (2004) discloses a single-hole transistor (SHT) in the form of an ultranarrow wire channel metal-oxide-semiconductor field-effect transistor (MOSFET).

Charge carrier transport can be controlled using other, different mechanisms.

For example, devices are known in which carrier transport is controlled, at least in part, by charge carrier spin. Well-known examples of these so-called “spintronic” devices include spin valves, based on the giant magnetoresistive effect (GMR), and magnetic tunnel junction (MTJ) devices. Generally, these devices comprise alternating layers of ferromagnetic and non-ferromagnetic material, the non-ferromagnetic material being metallic (in the case of a spin-valve) or insulating (in the case of MTJ device). Spintronic devices have several applications, including magnetic field sensors and magnetic random access memory (MRAM). A review of spin-based electronics and applications is given “Spintronics: A Spin-based Electronics Vision for the Future” by S. A. Wolf et al., Science, volume 294, pp. 1488 to 1495 (2001).

Attempts have been made to make single-electron transistors which also exhibit magnetoresistance effects.

For example, “Enhanced Magnetic Valve Effect and Magneto-Coulomb Oscillations in Ferro Magnetic Single Electron Transistor” by K. Ono, H. Shimada and Y. Ootuka, Journal of the Physical Society of Japan, vol. 66, No. 5, pp. 1261-1264 (1997) describes a single-electron transistor exhibiting Coulomb blockade oscillations induced by Zeeman coupling of electron spins to an external magnetic field. These magneto Coulomb blockade oscillations require application of magnetic fields of the order of a Tesla and do not lead to a non-volatile memory effect.

A low-field hysteretic magnetoresistance (MR) effect has been demonstrated in single-electron transistors where the relative magnetic configurations of the leads are switched from parallel to antiparallel. The sensitivity of the magnetoresistance to the gate voltage was attributed to resonant tunnelling effects through quantized energy levels in the island. Since in this case the magnetic field induced magnetization reorientation causes no shift in Q₀ the effect of the magnetic field is more subtle than that of the gate voltage, and variations in the source-drain current due to the magnetic field are much weaker than the gate-voltage induced Coulomb blockade oscillations

The present invention seeks to provide an improved single-charge tunnelling device, for example which can also be used as a memory device.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention there is provided a single-charge tunnelling device comprising first and second leads and a conductive island arranged such that charge is transferable from the first lead to the second lead via the conductive island, a gate for changing an electrostatic energy of the conductive island, wherein at least one of the first lead, second lead, island and gate comprises a ferromagnetic material which exhibits a change in chemical potential in response to a change in direction of magnetisation.

The first lead, the second lead and the island, and optionally the gate, may each comprise the same ferromagnetic material. The first lead, the second lead and the island, and optionally the gate, may be formed in a layer of the ferromagnetic material. The layer may have a constriction and the conductive island may be formed within the constriction.

Shapes of the first lead, the second lead and the island may be arranged such that magnetization of at least one of the first lead, second lead and island is forced along a direction transverse to magnetization of others of the first lead, second lead and island or is forced along a different direction from the other direction for which the chemical potentials are different.

The device may comprise at least two islands arranged such that charge is transferable from the first lead to the second lead via at least one of the at least two conductive islands.

The conductive island may have a charging energy and the change in direction of magnetization may causes a change in chemical potential of at least of the order of the charging energy.

At least two of the first lead, second lead and island may comprise a ferromagnetic material and there may be a net change in chemical potential in response to a change in direction of magnetization of at least one of the at least two of the first lead, second lead and island.

The change in chemical potential may be at least 1 meV, at least 6 meV or at least 9 meV.

The ferromagnetic material may be GaMnAs, such as Ga_(0.98)Mn_(0.02)As.

The ferromagnetic material may comprise an alloy including a rare earth metal, such as Dy, Er or Ho. The ferromagnetic material may comprise an alloy including a noble metal

The ferromagnetic material may comprise FePt, CoPt or CoPd.

According to a second aspect of the present invention there is provided a single-charge tunnelling device comprising first and second leads and a conductive island arranged such that charge is transferable from the first lead to the second lead via the conductive island, wherein at least one of the first lead, second lead and island comprises a ferromagnetic material which exhibits a change in chemical potential in response to a change in direction of magnetisation.

According to a third aspect of the present invention there is provided a non-volatile memory comprising the single-charge tunnelling device.

According to a fourth aspect of the present invention there is provided a magnetic field sensor comprising the single-charge tunnelling device.

According to a fifth aspect of the present invention there is provided a method of operating the single-charge tunnelling device, the method comprising applying a first bias to the gate, removing the first bias from the gate, measuring a first resistance between the leads, applying a second, different bias to the gate, removing the second bias from the gate, measuring a second resistance between the leads, such that the first and second resistances differ.

According to a sixth aspect of the present invention there is provided a method of operating the single-charge tunnelling device, the method comprising applying a first magnetic field, removing the first magnetic field, measuring a first resistance between the leads, applying a second, different magnetic field, removing the second magnetic field, measuring a second resistance between the leads; such that the first and second resistances differ.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings in which:

FIG. 1 is perspective schematic view of a single-electron transistor in accordance with certain embodiments of the present invention;

FIG. 2 shows electron-beam micrographs of the single-electron transistor shown in FIG. 1;

FIG. 3 is a schematic plan view of a Hall bar including the single-electron transistor 1 shown in FIG. 1 and a test structure;

FIG. 4 shows plots of resistance against magnetic field for the test structure shown in FIG. 3;

FIGS. 5 a and 5 b show plots of resistance against magnetic field for the single-electron transistor shown in FIG. 1;

FIGS. 6 a and 6 b show plots of resistance against magnetic field orientation for different gate voltages for the single-electron transistor shown in FIG. 1;

FIG. 7 shows a plot of resistance against magnetic field orientation for the single-electron transistor shown in FIG. 1;

FIG. 8 shows a circuit model for a single-electron transistor;

FIG. 9 illustrates current-voltage plots for the single-electron transistor shown in FIG. 1;

Referring to FIGS. 10 a and 10 b show contributions to Gibbs energy associated with the transfer of charge from a lead to an island of a single-electron transistor;

FIG. 11 shows plots of density-dependent chemical potentials with respect to uniaxial anisotropy modeled using a k.p kinetic-exchange model;

FIG. 12 shows a plot of Coulomb blockade conductance as a function of gate voltage for the single-electron transistor shown in FIG. 1;

FIG. 13 shows a plot of resistance as a function of gate bias and magnetic field strength for the single-electron transistor shown in FIG. 1;

FIG. 14 shows plots of resistance against magnetic field for the single-electron transistor shown in FIG. 1;

FIGS. 15 a to 15 c illustrate steps in a process of fabricating of the single-electron transistor shown in FIG. 1;

FIG. 16 shows Coulomb blockade oscillation curves for the single-electron transistor shown in FIG. 1;

FIG. 17 show plots of resistance against magnetic field for the single-electron transistor shown in FIG. 1;

FIGS. 18 a to 18 c show illustrative potential distributions and stable magnetization states for different magnetisations angles;

FIG. 19 illustrates electrical switching of states;

FIG. 20 is a greyscale plot of conductance as a function of magnetic field for the single-electron transistor shown in FIG. 1;

FIGS. 21 a and 21 b are conductance plots as a function of magnetic field for the single-electron transistor shown in FIG. 1;

FIG. 22 show plots of conductance against gate bias for B=0 T, B=−0.1 T, B=−0.022 T and B=−0.035 T for the single-electron transistor shown in FIG. 1;

FIG. 23 illustrates a process for manipulating and storing information using the single-electron transistor shown in FIG. 1;

FIG. 24 is a state table;

FIG. 25 is a schematic diagram of a generic device in accordance with certain embodiments of the present invention;

FIG. 26 shows a lateral conduction device in accordance with certain embodiments of the present invention;

FIG. 27 is a cross-section of the device shown in FIG. 26 taken along the line A-A′;

FIG. 28 illustrates a vertical conduction device in accordance with certain embodiments of the present invention;

FIG. 29 shows self-assembled islands;

FIG. 30 illustrates shape anisotropy;

FIG. 31 illustrates stabilization of magnetization of a ferromagnetic region in an external field; and

FIG. 32 illustrates a head in accordance with certain embodiments of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Device Structure

Referring to FIGS. 1 and 2, a single-electron transistor 1 in accordance with certain embodiments of the present invention has an elongated conductive channel 2 and a side gate 3 formed in a patterned layer 4 of (Ga,Mn)As by trench-isolation. A layer 5 of AlAs electrically isolates the channel 2 and the side gate 3 from a GaAs substrate 6. The channel 2 includes a constriction 7 disposed between wider portions which provide electrical leads 8, 9 to the constriction 7.

The (Ga,Mn)As layer 4 comprises 2% Mn, i.e. Ga_(0.98)Mn_(0.02)As, and has a thickness of 5 nm. The constriction 7 is 30 nm wide and 30 nm long. The channel 2 is 2 μm wide. The channel 2 and the gate 3 are separated by about 30 nm.

In the region of the constriction 7, potential fluctuations arising from disorder create at least one conductive island 10 and at least a pair of tunnel barriers 11 which weakly couple the island 10 to leads 8, 9 and/or adjacent islands 10.

As will be explained in more detail later, the single-electron transistor 1 is operable, in a first mode, as a transistor and, in a second mode, as non-volatile memory. However, before describing operation of the single-electron transistor 1, the magnetoresistance characteristics of a test structure 13 (FIG. 3) will first be described and compared with the magnetoresistance characteristics of the single-electron transistor 1.

Magnetoresistance Characteristics

Referring to FIG. 3, the single-electron transistor 1 and a test structure 13 share an elongate Hall bar 14 formed in the patterned (Ga,Mn)As layer 4 and has pairs of terminals 15 spaced at 10 μm intervals either side of the constriction 7. The longitudinal axis of the bar 14 is arranged along the [110] direction.

A voltage source 16 is arranged to provide a source-drain bias V_(SD) between ends of the bar 14. A current meter 17 is arranged to measure a source-drain current I through the bar 14. A first voltage meter 18 is configured to measure a potential difference V_(C) across the constriction 7 and a second voltage meter 19 is arranged to measure a potential difference V_(S) across the test structure 13. This arrangement allows the characteristics of the single-electron transistor 1 and the test structure 13 to be compared. A second voltage source 20 is arranged to apply a bias V_(G) to the gate 3 (with respect to ground).

A chip (not shown) on which the Hall bar 14 is fabricated is mounted on an insert (not shown) and placed in a cryostat (not shown) having a superconducting coil (not shown) and power supply (not shown) for applying a magnetic field (not shown). The insert includes connecting wires (not shown) for connecting the control and measurement system 16, 17, 18, 19, 20 outside the cryostat to the single-electron transistor 1 and test structure 13 within the cryostat.

The insert (not shown) has a tiltable support (not shown) on which the chip is mounted which allows the chip to be tilted with respect to the magnetic field. Thus, the magnetic field can be aligned parallel with or perpendicular to current flow I in the Hall bar 14.

—Magnetoresistance Characteristics for Test Structure 13—

Referring to FIG. 4, plots 21 ₁, 21 ₂, 22 ₁, 22 ₂, 23 of resistance R_(S) (=V_(S)/I) of the test structure 13 at V_(SD)=5 mV and temperature of 4.2° K are shown.

First and second plots 21 ₁, 21 ₂ show how resistance R_(S) varies as a function of magnetic field magnitude for a parallel magnetic field (i.e. B∥I) as the field is increased and decreased respectively. Third and fourth plots 22 ₁, 22 ₂ show how resistance R_(S) varies as a function of magnetic field magnitude for a perpendicular magnetic field (i.e. B⊥I) as the field is increased and decreased respectively. Finally, fifth plot 23 shows resistance R_(S) as a function of magnetic field orientation for a fixed, large magnetic field of 5 Tesla. Here, angle θ=90° corresponds to B∥I (and also to M⊥I at large fields).

The test structure 13 exhibits a high resistance state when magnetization is aligned with current I in the structure 13 and a low resistance state when magnetization is aligned perpendicular to current in the structure 13.

—Magnetoresistance Characteristics for Single-Electron Transistor 1—

Referring to FIGS. 5 a and 5 b, plots 24, 25 of resistance R_(C) (=V_(C)/I) of the constriction 7 of the single-electron transistor 1 at V_(SD)=5 mV and 4.2° K are shown.

In FIG. 5 a, the plot 24 shows how resistance R_(C) varies with gate voltage V_(G) and also with magnetic field strength when the field is aligned parallel with current flow (i.e. B∥I). In FIG. 5 b, the plot 25 shows how resistance R_(C) varies with gate voltage V_(G) and also orientation of magnetic field for a fixed, large magnetic field of 5 Tesla.

Similar to the test structure 13, the single-electron transistor 1 also shows high and low resistance states depending on whether magnetic field is aligned parallel with or perpendicular to current flow, i.e. anisotropic magnetoresistance (AMR) effect.

However, in the single-electron transistor 1, the anisotropic magnetoresistance not only depends on gate voltage V_(G), but also is greatly enhanced as seen, for example, at V_(G)=0.5 V. As will be explained in more detail later, this effect (herein referred to as the “Coulomb blockade anisotropic magneto resistance effect” or “CBAMR effect”) can be used to provide non-volatile memory functionality.

Referring to FIGS. 6 a and 6 b, plots 26, 27 ₁, 27 ₂, 27 ₃, 27 ₄, 27 ₅ of resistance R_(C) of the constriction 7 of the single-electron transistor 1 for different gate voltages V_(G) and orientations of magnetic field, at V_(SD)=5 mV and 4.2° K are shown.

The single-electron transistor 1 exhibits shifts in the Coulomb blockade oscillation pattern caused by changes in magnetization orientation. For example, the oscillations have a peak 28 at V_(G) =−0.4 V for θ=90° which moves to higher gate voltages with increasing θ and, for θ=130°, the

V_(G)=−0.4 V state becomes a minimum in the oscillatory resistance pattern.

Referring also to FIG. 7, a plot 29 of resistance R_(C) of the constriction for the single-electron transistor 1 for different orientations of magnetic field at V_(G)=−0.4 V and 4.2° K is shown.

Comparing the first plot 27 ₁ shown in FIG. 6 b with the plot 29 shown in FIG. 7, changes in the magnitude of resistance R_(C) arising from changes in gate voltage V_(G) are comparable to those arising from changes in magnetic field orientation.

—Single-Electron Transistor 1 Gate and Tunnel Barrier Parameters—

Before explaining the behaviour of the single-electron transistor 1 in detail, gate and tunnel barrier parameters for the single-electron transistor 1 can be estimated.

Referring to FIG. 8, a circuit model 30 for a single-electron transistor is shown. An island has a total capacitance C_(Σ)=2C=C_(G) which defines the Coulomb blockade charging energy e²/2C_(Σ).

Referring to FIG. 9, current-voltage plots 31, 32 for the single-electron transistor 1 at 4.2° K and 50° K are shown. The first plot 31 shows the single-electron transistor 1 in a Coulomb blockade regime. The second plot 32 shows the single-electron transistor 1 in an ohmic-conduction regime. From the current-voltage plot 31 at 4.2° K, the charging energy e²/2CΣ can be estimated to be of the order of a few meV from a position 33 at which current flows. The position 33 does not change if the transistor 1 is cooled to lower temperatures.

Referring again to FIG. 6 b, from any one of the resistance-gate voltage plots 27 ₁, 27 ₂, 27 ₃, 27 ₄, 27 ₅ the period of the Coulomb blockade oscillations e/C_(G) is of the order of ˜100 mV.

Using the characteristics shown in FIGS. 6 b and 9, values of C_(Σ), C_(G) and C can be estimated. This shows that the lead-island capacitance C is approximately 100 times larger than the gate capacitance C_(G). This is consistent with the geometry, dimensions and materials of the single-electron transistor 1, namely the gate 2 and constriction 7 being separated by 30 nm and the dielectric constant of the tunnel barriers having a value of 12.85, i.e. using a value for GaAs.

—Coulomb Blockade Anisotropic Magnetoresistance (CBAMR) Effect—

The following is provided by way of an explanation of the behavior of the single-electron transistor 1.

As explained earlier, the single-electron transistor 1 exhibits an enhanced anisotropic magnetoresistance (AMR) effect. The microscopic origin of this effect is considered to occur due to anisotropies in chemical potential μ arising from the spin-orbit coupled band structure of (Ga,Mn)As.

Referring to FIG. 10, first and second energy diagrams 34 ₁, 34 ₂ show contributions to the Gibbs energy U associated with the transfer of charge Q from the lead 8 to the island 10.

The Gibbs energy U can be expressed as the sum of the internal, electrostatic charging energy term and the term associated with, in general, different chemical potentials of the lead 8 and of the island 10, namely:

U=∫ ₀ ^(Q) dQ′ΔV _(D)(Q′)+QΔμ/e  (1)ps

where

ΔV _(D)(Q)=(Q+C _(G) V _(G))/C _(Σ.)

The carrier concentration is non-uniform, which suggests that the difference Δμ between chemical potentials of the lead 8 and of the island 10 in the constriction 7 depends on the magnetization orientation. The difference Δμ is considered to increase with decreasing doping density in (Ga,Mn)As.

The Gibbs energy U is minimized for Q₀=−C_(G)(V_(G)+V_(M)), where the magnetization orientation dependent shift of the Coulomb blockade oscillations is given by V_(M)=CΣ/C_(G)Δμ(M)/e. Since |C_(G)V_(M)| has to be of order |e| to cause a marked shift in the oscillation pattern, the corresponding |Δμ(M)| has to be similar to e²/C_(Σ), i.e., of the order of the island single electron charging energy.

As shown earlier, the single electron charging energy is estimated to be of order of a few meV. Theoretical calculation (FIG. 11) confirms that chemical potential variation due to magnetization reorientation is also of the order few meV and therefore can cause CBAMR effect.

Unlike the ohmic or tunnelling anisotropic magnetoresistance, whose magnitude scales with the relative anisotropies in the group velocity (and scattering lifetimes) or the tunnelling density of states, the CBAMR effect occurs when the absolute magnitude of the change of the chemical potential is comparable to the single electron charging energy. When this occurs, magnetization rotation-induced variations in resistance are of the size of the SET Coulomb blockade oscillations.

Although the single-electron transistor 1 described earlier is formed in a thin layer of (Ga,Mn)As, other ferromagnetic material exhibiting strong spin-orbit coupling may be used. For example, chemical potential variations due to magnetization rotations may reach 10 meV in a FePt ordered alloy (FIG. 11). Thus, the single-electron transistor may be formed in thin layers of a material comprising a transition metal and a noble metal may be used.

Furthermore, the CBAMR effect can occur whenever there is a difference in chemical potential anisotropies in different parts 2, 8, 9, 10 of the single-electron transistor 1. This can be arranged by fabricating the leads 8, 9, gate 2 and island 10 from the same ferromagnetic material, but with different shape anisotropies leading to different magnetization reorientation fields or by fabricating at least one of the leads 8, 9, gate 2 and island 10 from a different ferromagnetic material exhibiting strong spin-orbit coupling.

—Magnetic Anisotropy in Thin GaMnAs Films—

The (Ga,Mn)As layer 4 (FIG. 1) exhibits in-plane cubic anisotropy with <100> easy axes arising from compressive biaxial strain.

The (Ga,Mn)As layer 4 (FIG. 1) also exhibits a pronounced uniaxial anisotropy along one of the cubic hard axes <110> which strongly depends on the carrier density.

The uniaxial anisotropy can be explained in terms of the p-d Zener model of the ferromagnetism assuming a small trigonal-like distortion. Such a distortion may be associated with strains due to the etching of the lithographically defined transistor 1 or may result from a non-isotropic Mn distribution.

Thus, structures patterned from ultra-thin GaMnAs film exhibit a strong uniaxial anisotropy with easy axis along [1-10] direction which corresponds to the direction in plane and perpendicular to the bar 14.

FIG. 11 shows a plots 35 ₁, 35 ₂ of density-dependent chemical potentials with respect to uniaxial anisotropy modeled using a k.p kinetic-exchange model by assuming a small (0.1%) shear strain for Ga_(0.98)Mn_(0.02)As and Ga_(0.95)Mn_(0.05)As. Although the model used does not allow the full anisotropy of the work function (chemical potential measured from the vacuum level) to be calculated, it nevertheless illustrates variations of the chemical potential of a few mV for in-plane magnetization rotation.

FIG. 11 also shows (in an inset) chemical potentials 36 ₁, 36 ₂ for CoPt and FePt. CoPt or FePt show larger chemical potential anisotropies and use of these alloys as a ferromagnetic material may allow devices in accordance with certain embodiments of the invention to exhibit CMAMR effect at higher temperatures.

—Single-Electron Transistor 1 Characteristics—

Referring to FIG. 12, a plot 37 of Coulomb blockade conductance I/V_(C) of the constriction 7 of the single-electron transistor 1 as a function of gate voltage V_(G) at 4.2° K is shown. The plot 37 shows so-called “conductance diamonds” 38 arising from Coulomb blockade oscillations. The Coulomb blockade oscillations disappear at approximately 10° K.

Referring to FIG. 13, a plot 39 of resistance R_(C)(=V_(C)/I) of the constriction 7 of the single-electron transistor 1 as a function of gate bias V_(G) and magnetic field strength at V_(SD)=3 mV and 4.2° K is shown. The magnetic field is applied in the plane of the (Ga,Mn)As layer 4, but perpendicular to the longitudinal direction of the bar 14 (FIG. 2) and channel 2 (FIG. 1). The single-electron transistor 1 exhibits high electro- and magneto-sensitivity.

Referring also to FIG. 14, which shows forward and reverse sweep plots 40 ₁, 40 ₂, 41 ₁, 41 ₂ of resistance R_(C)(=V_(C)/I), the resistance of the constriction 7 drops by approximately 100% at V_(G)=0.94 V at B=20 mT and rises by more than 1000% at V_(G)=1.15 V. The resistance changes are associated with rotations of (Ga,Mn)As magnetization.

Device Fabrication

Referring to FIGS. 15 a to 15 c, fabrication of the Hall bar 14 (FIG. 3) including the single-electron transistor 1 will now be described.

Referring to FIGS. 15 a, the Hall bar 14 (FIG. 3) is fabricated from an ultra-thin (5 nm) Ga_(0.98)Mn_(0.02)As epilayer 4′ grown along the [001] crystal axis on a AlAs 5′ buffer layer on a GaAs substrate 6 by low-temperature molecular beam epitaxy and reference is made to “High-quality GaMnAs films grown with arsenic dimers” by R. P. Campion, K. W. Edmonds, L. X. Zhao, K. Y. Wang, C. T. Foxon, B. L. Gallagher and C. R. Staddon, Journal of Crystal Growth, volume 247, p 42 (2003).

Due to the high reactivity of the GaMnAs layer to alkaline developers used in optical lithography, Hall bar 14 is defined using electron-beam lithography using a poly-methyl-methacrylate (PMMA) resist developed using ultrasound in a methyl isobutyl ketone/isopropanol 1:3 mixture at 25° C.

Thermally-evaporated, high-electron-contrast Cr/Au registration marks (not shown) having thicknesses of 20 nm and 60 nm respectively are patterned by lift-off using 1 μm-thick resist (not shown) and ˜250 nm electron-beam diameter. A 30 s dip in 10% HCl solution is used prior to evaporation to assist adhesion of metal without unduly damaging the GaMnAs.

A ˜200 nm-thick layer of resist (not shown) is applied to the surface 42 of the Ga_(0.98)Mn_(0.02)As epilayer 4′. The finest features are defined using an electron-beam (not shown) having a ˜15 nm beam diameter and ˜5 pA current, with on-chip focusing at adjacent registration marks. Less-critical areas (not shown) are defined in the same resist by a ˜250 nm beam at ˜1 nA. The high-resolution regions are arranged to be as small as possible to minimise write time and pattern drift.

Referring to FIG. 15 b, the resist is developed to leave a patterned resist layer 43 as an etch mask.

Referring to FIG. 15 c, reactive-ion etching (RIE) is used for trench isolation. Any RIE-related conductivity impairment is expected to be minimal compared with the high conductivity of the GaMnAs. The pressure in the RIE chamber (not shown) is 20 mTorr, with 20 sccm flow of both SiCl₄ and Ar to provide the required mix of physical and chemical etch action suitable for removing both GaAs and manganese. A typical etch of 10-15 s at 100 W yielded a trench 44 having a depth of 20-30 nm, safely through the GaMnAs layer.

Cr/Au (20 nm/300 nm) bond pads are thermally evaporated, again preceded by an adhesion dip in HCl solution. The bond pads form a low-resistance electrical contact to the GaMnAs layer and no separate ohmic metallization is required.

In this example, devices are arranged in a Hall-bar layout aligned along [110] direction, with a 2 μm-wide channel and three pairs of Hall sensor terminals of 500 nm width at 10 μm intervals either side of the constriction. However, other arrangements can be used.

Device Operation

As explained earlier, the single-electron transistor 1 is sensitive to both electric and magnetic fields. Low-field hysteretic shifts in the Coulomb blockade oscillations can be induced in the transistor 1. Furthermore, the transistor 1 exhibits non-volatile memory effect with an “on” state resistance of order ˜1 MΩ and an “off” state resistance of the order of ˜10 MΩ (or higher).

In conventional, non-magnetic single-electron transistors, the Coulomb blockade “on” (low-resistance) and “off” (high-resistance) states are used to represent logical “1” and “0” and the switching between the two states can be realized by applying the gate voltage, similar to conventional field-effect transistors.

The single-electron transistor 1 can be addressed not only electrically as for a conventional, non-magnetic single-electron transistor, but also magnetically with comparable “on” to “off” resistance ratios in electric and magnetic modes.

Furthermore, magnetization can be re-orientated and, thus, the state of the device changed between “0” and “1” either magnetically or electrically, as shall now be described.

—Magnetic Field Induced Switching—

Referring to FIG. 16, two Coulomb blockade oscillation curves45 ₁, 45 ₂ are shown corresponding to magnetizations M₀ and M₁ of, in this case, one of the islands 10 (FIG. 1).

Referring also to FIG. 17, magnetization M₀ can be set by performing a small loop in the magnetic field, B→B₀→0 where B₀ is larger than the first switching field B_(C1) and smaller than the second switching field B_(C2) and magnetization M₁ can be achieved by performing the large filed-loop, B→B₁→0 where B₁<−B_(C2).

Assuming the system is in the M₁ state, the voltage V_(G0) corresponds to “0” and V_(G1) to “1” in the electric mode. Conversely, fixing the gate voltage at V_(G1), the switching from “1” to “0” can be performed by changing the magnetic state from M₁ to M₀. Due to the hysteresis, the magnetic mode represents a non-volatile memory effect.

Electric Field Induced Switching

Referring again to FIG. 1, in the single-electron transistor 1, the gate 2 can be used to vary the carrier density. As explained earlier, uniaxial anisotropy can depend on, among other things, the carrier density. Therefore, the gate 2 can be used to control unixial anisotropy and, thus, whether unixial anisotropy or biaxial (or cubic) anisotropy dominates.

FIGS. 18 a to 18 c show first, second and third illustrative potential distributions 46 ₁, 46 ₂, 46 ₃ and stable magnetization states M₀, −M₀, M₁, −M₁ for the island 10 at different magnetisations angles for three different gate voltages, namely V_(G)=V1, V_(G)=0 and V_(G)=V2 respectively. The angles θ=0°, 45°, 90°, 135° and 180° may correspond, for example to [1-10], [100], [110], [010], and [−110].

Referring to FIG. 18 a, uniaxial anisotropy is maintained (or even amplified), while cubic anisotropy is suppressed, at V_(G)=V1, thereby favouring magnetization M₁.

Referring to FIG. 18 b, the Mn doping concentration may be such that well-isolated energy minima for both uniaxial and cubic anisotropy exist at V_(G)=0.

Referring to FIG. 18 c, cubic anisotropy dominates over the uniaxial anisotropy at V_(G)=V2, thereby favouring magnetization M₀.

Thus, applying either V_(G)=V1 or V2 causes a change in magnetisation. However, removing the applied V_(G), the magnetisation remains.

Referring to FIG. 19, plots 47, 48 show how changes in gate voltage V_(G) result in a change of measurable resistance R_(C) with time.

Referring to FIG. 20, a greyscale plot 49 of conductance (=I/V_(C)) against gate voltage V_(G) and against in-plane, parallel magnetic field strength at V_(SD)=3mV and at 4.2 K is shown. The applied field orientation corresponds to one of the magnetic hard axes in this system. The dashed line 50 shows critical reorientation field which is strongly gate bias dependent.

Referring to FIGS. 21 a and 21 b, conductance plots 51 ₁, 51 ₂, 52 ₁, 52 ₂ at V_(G)=−0.96V and at V_(G)=0.97V are shown. The plots highlight a substantial decrease in the first critical reorientation field from about 0.04 T at V_(G)=−0.96V to less than 0.02 T at V_(G)=0.97V.

Referring FIG. 22, plots 53 ₁, 53 ₂, 53 ₃, 53 ₄ showing variation of conductance with gate bias for B=0 T, B=−0.1 T, B=−0.022 T and B=−0.035 T respectively are shown.

At B=OT, the island 10 remains in magnetization state M₀ over the gate voltage range between V_(G)=−1V to 1V. Likewise, at B=−0.1 T, the island 10 remains in magnetization state M₁ over the gate voltage range.

However, at intermediate field strengths B=−0.022 T and B=−0.035 T, the island 10 passes through a transition from M₀ to M₁ at critical gate voltages of about 0.6V and −0.5V respectively.

Thus, electric field assisted magnetization reorientations are observed at lower gate voltages compared with conventional field effect transistor.

Referring to FIGS. 23 and 24, a process for manipulating and storing information using the single-electron transistor 1 is shown. FIG. 24 shows a table with instructions for manipulating states. At V_(G0), the system is in the low-resistance (“1”) state if the magnetization M=M₁, but in the high-resistance state if M=M₀. At V_(G1), the opposite relation applies. Thus, the transistor characteristics can be inverted.

Other Devices

In the single-electron transistor 1 described earlier, the chemical potentials of the gate 2, leads 8, 9 and islands 10 depend on their respective magnetization orientations. The chemical potentials differ relative to one another to such a degree that the difference is of the order of the charging energy of the island and of the order or larger than k_(B)T.

However, it is not necessary that each region 2, 8, 9, 10 or element of the transistor 1 be ferromagnetic. For example, only one or more of these regions 2, 8, 9, 10 need. be ferromagnetic.

Furthermore, lead(s) and island(s) can be formed from the same ferromagnetic material, but the magnetization may be fixed and/or stabilized along a given direction, for example by shape anisotropy or exchange coupled structures, for some of these regions such as for one or more of the leads.

—Generic Device—

Referring to FIG. 25, a device 54 in accordance with certain embodiments of the present invention comprises first and second conductive leads 55, 56, at least one island 57 and, optionally, at least one gate 58. At least one part 55, 56, 57, 58 of the device 54 comprises ferromagnetic material and the magnetization orientation of at least one can be changed by external magnetic field or a gate 58. In this example, all conductive parts 55, 56, 57, 58 of the device 54 are ferromagnetic and have magnetisations M_(L1), M_(L2), M_(i), M_(G). Thus, chemical potentials □_(L1), □_(L2), □_(J), □_(G) of the conductive parts 55, 56, 57, 58 depend upon magnetisations M_(L1), M_(L2), M_(i), M_(G), i.e. □_(L1)(M_(L)), □_(L2)(M_(L2)), □_(i)(M_(i)), □_(G)(M_(G)).

For simplicity, only one island 57 is shown and described. However, the device 54 may include more than one island, for example in a multiple tunnel junction (MTJ) arrangement, similar to that described in EP-A-0674798.

The island 57 is weakly coupled to the leads 55, 56 via tunnel barriers 59, 60. The tunnel barriers 59, 60 each have a resistance which is larger than the inverse of the quantum conductance 2e²/h (where h is the Planck's constant) of about 13 kΩ for localising electrons.

To operate at a given temperature T, the charging energy e²/2C_(ISLAND) of the island is larger than thermal energy k_(b)T (where k_(b) is Boltzmann's constant). Thus, to operate at 77° K (i.e. the boiling point of liquid nitrogen) or at around 293° K (i.e. room temperature), the island capacitance C_(ISLAND) is less than about 12 aF and 3 aF respectively.

The relative change of chemical potential between different parts 55, 56, 57, 58 of the device 54 before and after magnetization re-orientation is of the order of the charging energy, for example about 6 meV and 25 meV for 77° K and 293° K.

The device 54 may be fabricated, for example from an epilayer of ferromagnetic semiconductor in a similar way to single-electron transistor 1 described earlier or from successively-evaporated layers of ferromagnetic material in a similar way to that described in “Enhanced Magnetic Valve Effect and Magneto-Coulomb Oscillations in Ferro Magnetic Single Electron Transistor” supra.

—Lateral Device—

Referring to FIGS. 26 and 27, the device 54 may be formed in a single layer 61 of ferromagnetic material showing strong magnetic anisotropy. The layer 61 is grown on a layer 62 of insulating material on a conductive substrate 63 which provides a (back) gate 58 and controlled via contact 64. The ferromagnetic material layer 61 may be formed of (Ga,Mn)As and may have a thickness of 5 nm. The insulating layer 62 may be AlAs and may have a thickness of 20 nm. The conductive substrate 63 may be n-GaAs.

The island 57 may be defined by patterning narrow barriers by locally oxidizing the ferromagnetic material layer 61 using a scanning tunnelling microscope (STM) or atomic force microscope (AFM), for example as described in “Room temperature operation of a single electron transistor made by the scanning tunnelling microscope nanooxidation process for the TiO_(x)/Ti system” supra., by dry etching using a focused ion beam (FIB) or by etching using direct contact lithography and (wet or dry) etching.

Shape anisotropy is used to force the magnetization of the island 57 and lead 56 along x-direction and the magnetization of lead 55 along y- or −y-direction. Applying an external magnetic field B_(EXT) allows, for example the magnetisation M_(i) of the island 57 to align along the direction of B_(EXT) .

Alternatively, the device 54 may be arranged such that a magnetization M_(L1), M_(L2) in one of the leads 55, 56 rotates with respect to the magnetization M_(L1), M_(L2), M_(i) of the other lead 55, 56 and the island 57.

—Vertical Device—

Referring to FIGS. 26 and 27, the device 54 may be formed using plural overlying layers 65, 66, 67, 68, 69 and arranged as a pillar 70 with an annular gate arrangement 71. The pillar 70 has a diameter less than 50 nm and may be defined by electron-beam lithography and anisotropic dry etching.

The leads 55, 56 may be formed from non-ferromagnetic material, such as GaAs, the tunnel barriers 59, 60 may be formed from an insulating material, such as AlAs or AlGaAs, and the island(s) 57 may be formed from a ferromagnetic material, such as (Ga,Mn)As.

Alternatively, the leads 55, 56 may be formed from ferromagnetic material, such as GaAs, the tunnel barriers 59, 60 may be formed from an insulating material, such as AlAs or AlGaAs, and the island(s) 57 may be formed from a ferromagnetic material, such as (Ga,Mn)As, on non-ferromagnetic material, such as InGaAs.

The annular gate arrangement 71 comprises a concentric inner insulating layer 72 and a concentric outer gate 58. The insulating layer 72 may be formed from AlAs and the gate 58 may be formed from (ferromagnetic) GaMnAs or (non-ferromagnetic) GaAs, for example grown by MBE. Alternatively, the insulating layer 72 may be formed from Si₃N₄ deposited by CVD or sputtering and the gate 58 may be formed from (ferromagnetic) FePt or (non-ferromagnetic) Al deposited by sputtering or thermal evaporation.

Referring to FIG. 29, the island(s) 57 may be self-assembled by growing a thin layer 67′ of semiconducting material, such as InGaAs, by molecular beam epitaxy (MBE) in Stranski-Krastanov growth mode on a first insulting material layer 66′, then growing the second insulting material layer 67′. Thus, the island(s) 57 are embedded within insulting material.

As explained earlier, the leads 55, 56 and/or the island(s) 57 may be ferromagnetic. The thermal stability of the island magnetization is not necessarily required if an external magnetic field B_(EXT) stabilizes the island magnetization along its direction. The external magnetic field B_(EXT) maybe a field which is being sensed.

Referring to FIG. 30, shape anisotropy can arise from the interaction between the magnetic moments of a magnetic layer and a demagnetizing field, generated by the magnetic moments themselves. Therefore, the shape anisotropy favours an in-plane orientation of the magnetization M and depends also on the surrounding shape 72 of the ferromagnetic layer.

Referring to FIG. 31, a magnetic field sensitive ferromagnetic region, such as the island 57, might be so small that the magnetization at zero-applied magnetic field H_(EXT)=0 becomes thermally unstable. Notwithstanding this, a sensed external field can stabilize its magnetization via the Zeeman effect along the field direction. The corresponding Zeeman energy E_(z)˜Ms H_(EXT)V_(FM) is of the order of 1 meV/Oe for typical metal ferromagnets with saturation magnetization M_(s) of the order of 10 ³ emu/cm³ and by assuming a volume of the ferromagnetic region of (10×10×5) nm³.

—Ferromagnetic Materials—

In some embodiments of the present invention, ferromagnetic regions may be formed from a dilute magnetic semiconductor (DMS). However, the ferromagnetic regions may be formed from ferromagnetic metals and alloys.

Some ferromagnetic materials, such as FePt, CoPt and CoPd, ordered alloys, provide strong spin-orbit coupling. In these systems, the transition metal produces large exchange splitting resulting in the Curie temperatures well above room temperature, while the heavy elements of Pt substantially increase the strength of spin-orbit coupling in the band structure of the alloy. Calculated chemical potential anisotropies for FePt and CoPt are shown in FIG. 11.

Other ferromagnetic materials may be used such as alloys including rare earth metals with occupied 4f electron-levels, such as Dy, Er and Ho.

—Hard Disk Head—

Referring to FIG. 32, the device 54 may be formed using plural overlying layers 72, 73, 74, 75, 76 and having a combined top and side gate arrangement 77.

The first and second conducting layers 73, 75 provide leads 55, 56 and may be formed from non-ferromagnetic conductive material, such as W or Ti. An insulating layer 73, sandwiched between the conducting layers 73, 75, includes ferromagnetic conducting islands 57 and provides tunnel barriers 59, 60. The insulating layer 73 may be formed from Si₃N₄ or SiO₂ and the conducting islands 57 may be formed from ferromagnetic material, such as CoPt or FePd. The ferromagnetic conducting islands 57 have a diameter, d, of the order of 1 nm, for example between 2 and 5 nm. The insulating layer 73 has a thickness t, for example, such that tunnel barriers 59, 60 have a thickness, s, of the between 3 and 7 nm for Si₃N₄ and 1 and 4 nm SiO₂, where s=0.5(t−d). The first and second conducting layers 73, 75 have a thickness of the order of 10 nm.

The gate 58 is formed of non-ferromagnetic conductive material, such as W or Ti, and is isolated by a gate insulator 76, such as Si₃N₄ or SiO₂. The device 54 is formed on substrate 72 of silicon or quartz.

Devices according to certain embodiments of the present invention can provide combined spintronic and single-electronic functionality, which can allow the devices to operate as a transistor and/or as a non-volatile memory.

A three-terminal device according to certain embodiments of the present invention can operate with transistor characteristics corresponding to a n-channel and/or a p-channel field effect transistor. Switching between n-channel and p-channel characteristics is achieved by operating the device in its “magnetic mode” which can be realized by applying either a magnetic field or an electric field.

Furthermore, combined functionalities allow the simple realization of logic functions, such as controlled NOT operation.

Devices according to certain embodiments of the present invention can provide signal amplification without any additional transistors. Therefore, non-volatile memory can be realised with fewer additional electronic components.

Devices according to certain embodiments of the present invention can consume little power since transport is based on single electrons.

Devices according to certain embodiments of the present invention can exhibit thermal stability since the ferromagnetic regions of the device can be provided using larger parts of the devices, such as leads and gates. This can help to ameliorate thermal instability arising from superparamagnetic limitation and magnetic noise, which may be problematic for MRAM and HDD sensor applications as devices are scaled down.

Unlike conventional GMR- and TMR-devices where the relative orientation between two ferromagnetic regions define the resistance state of the device, devices according to certain embodiments of the present invention can operate (in a “magnetic mode”) by reorienting magnetization of the magnetic region(s) solely with respect to their crystalline orientation and/or current direction. Thus, the state of the device operated in a “magnetic mode” can therefore be defined by the magnetization orientation of a single magnetic region. The use of an additional “pinned layer”, necessary in conventional GMR- and TMR-devices to provide thermal stability, is not required.

For sensors according to certain embodiments of the present invention, even though the magnetic field sensitive ferromagnetic region may be so small that the magnetization at zero-applied magnetic field H_(EXT)=0 becomes thermally unstable, a sensed external field can stabilize the magnetization via the Zeeman effect along the field direction.

If a sensor according to certain embodiments of the present invention is operated in a magnetic mode, it can have ultra-high magneto-sensitivity.

Devices according to certain embodiments of the present invention can exhibit non-volatile memory function using electrical field induced magnetization reversal.

Devices according to certain embodiments of the present invention can have a simple device structure in which parts of the device, such as gate, leads and island(s), can be made from a single patterned material layer. Furthermore, the sizes of the devices can be scaled.

It will be appreciated that many modifications may be made to the embodiments hereinbefore described. For example, the ferromagnetic layer may have a different thickness, for example between 5 and 20 nm. Ferromagnetic regions may be placed in close proximity to non-ferromagnetic regions so that non-ferromagnetic regions become also polarized with respect to the magnetization orientation of the ferromagnetic regions. Devices may operate based on electron or hole transfer. A capping layer may be used to protect the GaMnAs layer. 

1. A magnetoresistance single-charge tunnelling device comprising: first and second leads; a conductive island having a charging energy of at least 1 meV and arranged such that charge is transferable from the first lead to the second lead via the conductive island; and a gate for changing an electrostatic energy of the conductive island; wherein at least one, but not all, of said first lead, second lead, island and the gate comprises a ferromagnetic material which includes a rare earth element and/or a transition metal; wherein (i) the first and second leads are ferromagnetic but are configured such that one is not pinned relative to the another, (ii) the first or second lead is not ferromagnetic, or (iii) the first and second leads are not ferromagnetic; and wherein the single-charge tunnelling device exhibits an anisotropic magnetoresistance effect.
 2. A device according to claim 1 wherein the island is ferromagnetic.
 3. A device according to claim 1, wherein the gate is ferromagnetic.
 4. A device according to claim 1, wherein said rare earth metal is Dy, Er or Ho.
 5. A device according to claim 1, wherein said transition metal is a noble metal.
 6. A device according to claim 5, wherein the noble metal is Pt or Pd.
 7. A device according to claim 1, wherein the ferromagnetic material comprises Fe or Co.
 8. A device according to claim 1, comprising at least two islands arranged such that charge is transferable from the first lead to the second lead via at least one of the at least two conductive islands.
 9. A device according claim 1, wherein a one of the first lead, second lead, island or gate which is ferromagnetic exhibits a change in chemical potential which is at least 6 meV or at least 9 meV in response to rotation of magnetization from a first orientation to a second orientation which is not parallel or anti-parallel to the first orientation.
 10. A non-volatile memory comprising a device according to claim
 1. 11. A magnetic field sensor comprising a device according to claim
 1. 12. Apparatus, comprising: a device according to claim 1; and a magnetic field source which is configured to apply a magnetic field to the single-charge tunnelling device such that magnetization is rotated from a first orientation to a second orientation which is not parallel or anti-parallel to the first orientation.
 13. A magnetoresistance single-charge tunnelling device comprising: first and second leads; and a conductive island having a charging energy of at least 1 meV and arranged such that charge is transferable from the first lead to the second lead via the conductive island; wherein at least one, but not all, of the first lead, second lead and island comprises a ferromagnetic material which includes a rare earth element and/or a transition metal, wherein i) the first and second leads are ferromagnetic but are configured such that one is not pinned relative to the another, (ii) the first or second lead is not ferromagnetic, or (iii) the first and second leads are not ferromagnetic; and wherein the single-charge tunnelling device exhibits an anisotropic magnetoresistance effect.
 14. A non-volatile memory comprising a device according to claim
 13. 15. A magnetic field sensor comprising a device according to claim
 13. 16. Apparatus, comprising: a device according to claim 13; and a magnetic field source which is configured to apply a magnetic field to the single-charge tunnelling device such that magnetization is rotated from a first orientation to a second orientation which is not parallel or anti-parallel to the first orientation.
 17. A method of operating a single-charge tunnelling device comprising first and second leads, a conductive island having a charging energy of at least 1 meV and arranged such that charge is transferable from the first lead to the second lead via the conductive island and a gate for changing an electrostatic energy of the conductive island, at least one, but not all, of said first lead, second lead, island and the gate comprises a ferromagnetic material includes a rare earth element and/or a transition metal, wherein (i) the first and second leads are ferromagnetic but are configured such that one is not pinned relative to the another, (ii) the first or second lead is not ferromagnetic, or (iii) the first and second leads are not ferromagnetic, and wherein the single-charge tunnelling device exhibits an anisotropic magnetoresistance effect, the method comprising: applying a first bias to the gate; removing said first bias from the gate; measuring a first resistance between the leads; applying a second, different bias to the gate; removing said second bias from the gate; and measuring a second resistance between the leads such that the first and second resistances differ.
 18. A method according to claim 17, wherein applying the first bias causes magnetization to be rotated from the first orientation to the second orientation and applying the second bias causes magnetization to be rotated from the second orientation to a third orientation which is not parallel or anti-parallel to the first orientation.
 19. A method of operating a single-charge tunnelling device comprising first and second leads, a conductive island having a charging energy of at least 1 meV and arranged such that charge is transferable from the first lead to the second lead via the conductive island, at least one, but not all, of said first lead, second lead and island comprises a ferromagnetic material includes a rare earth element and/or a transition metal, wherein (i) the first and second leads are ferromagnetic but are configured such that one is not pinned relative to the another, (ii) the first or second lead is not ferromagnetic, or (iii) the first and second leads are not ferromagnetic and wherein the single-charge tunnelling device exhibits an anisotropic magnetoresistance effect, the method comprising: applying a first magnetic field; removing the first magnetic field; measuring a first resistance between the leads; applying a second, different magnetic field; removing the second magnetic field; and measuring a second resistance between the leads such that the first and second resistances differ.
 20. A method according to claim 19, wherein applying the first magnetic field causes magnetization to be rotated from the first orientation to the second orientation and applying the second magnetic field causes magnetization to be rotated from the second orientation to a third orientation which is not parallel or anti-parallel to the first orientation. 